UPC CFI 132/2024 – Total Semiconductor, LLC v Texas Instruments Incorporation, Texas Instruments Deutschland GmbH, Texas Instruments EMEA Sales GmbH

Expert Commentary

Full Decision Text

1 Local Division Mannheim UPC CFI 132/2024 Decision of the Court of First Instance of the Unified Patent Court Local Division Mannheim delivered on 9 October 2025 concerning EP 2 746 967 HEADNOTES: 1. In an infringement action, if the defendant disputes the implementation of a feature of the patent claim in a sufficiently substantiated manner, the claimant must submit specific facts about the design of the attacked embodiment, which, if these facts are proven, would lead to the assessment that the feature in question is implemented. The required degree of specification and substantiation depends on the degree of substantiation with which the defendant disputes the implementation. 2. Regularly, it cannot be expected from a defendant to defend himself against an assertion of indirect infringement that is raised in the oral hearing for the first time on the spot. In consequence, granting leave for such an amendment is regularly to be excluded, according to R. 263.2 (b) RoP and the right to defence. 3. When invoking general common knowledge (GCK) with regard to a certain subset of the features of a patent claim, it is not sufficient that all individual elements for themselves may be part of the GCK. Rather, the specific combination thereof as laid down in the patent claim has to be part of the GCK as well. 4. When relying on the allegation that the skilled person would arrive at a certain design that realizes a subset of the features of the patent claim when applying general known principles and combining general known elements, it has to be demonstrated that the skilled person would inevitably arrive at such design without applying inventive steps. KEYWORDS: Required degree of specification and substantiation with regard to the implementation of a disputed feature by the attacked embodiment; R. 263.2 (b) RoP; amendment of an infringement action during the oral hearing; inventive step involving general common knowledge 2 CLAIMANT Total Semiconductor, LLC - 101 E. Park Blvd., Ste 600 - 75074 - Plano, Texas – US Represented by Thomas Lynker DEFENDANTS 1) Texas Instruments Incorporation - 12500 TI Blvd - 75243 - Dallas – US Represented by Klaus Haft 2) Texas Instruments Deutschland GmbH - Haggertystr. 1 - 85356 - Freising – DE Represented by Klaus Haft 3) Texas Instruments EMEA Sales GmbH - Haggertystr. 1 - 85356 - Freising – DE Represented by Klaus Haft PATENT AT ISSUE European Patent No. EP 2 746 957 PANEL/DEVISION: Panel of the Local Division in Mannheim DECIDING JUDGES: This decision is delivered by the presiding judge Tochtermann, the judge-rapporteur Böttcher, the legally qualified judge Zana and the technically qualified judge Scilletta. LANGUAGE OF PROCEEDINGS: English SUBJECT-MATTER OF THE PROCEEDINGS: Patent infringement DATE OF THE ORAL HEARING: 22 July 2025 3 SUMMARY OF FACTS: 1. Claimant is suing Defendants for the alleged infringement of EP 2 746 957 B1 which relates to an intelligent interrupt distributor. The granting of the patent-in-suit was published on 11 July 2018. It was filed on 12 December 2013, claiming the priority of the patent application US 201213725698 of 21 December 2012. Claimant, a licensing company based in Texas, USA, is registered as proprietor of the patent-in-suit which is in force in France and Germany (Exhibit C 2). For these contracting member states to the UPCA, Claimant who allegedly acquired the patent-in-suit from the original owner and applicant NXP B.V., a semiconductor company based in the Netherlands, seeks injunctive relief, a declaration on infringement, recall/definite removal, destruction, communication of information and a declaration on Defendants’ liability for damages. 2. Claim 1 of the patent-in-suit as granted read as follows in the language of the patent: A multiprocessor system (300) comprising: a first processor (310); a second processor (320) coupled to the first processor by a first bus (340); a second bus (345) coupled to the first bus (340); a clock gating unit (390) directly coupled to the first processor and the second processor; a first and second peripheral device (354,355) coupled to the second bus; and an intelligent interrupt distributor (350) coupled to the first bus and directly coupled to the first and second processor by an interrupt bus (315) and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating unit, wherein the intelligent interrupt distributor is operable such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt bus to one of the first and the second processors which is in an idle state, and wherein the intelligent interrupt distributor adjusts an operating frequency and voltage of the first and the second processors by sending commands to the clock gating unit to main- tain a throughput that is the same as that for an equivalent single processor system. 3. Defendant 1 is an international semiconductor company based in Texas, USA. Defendants 2 and 3 belong the Defendant’s 1 group of companies. Defendant 2 manufactures semiconductor pre-products in its fabrication facility in Freising, Germany. Defendant 3 conducts sales activities inter alia on the markets of France and Germany. 4. In its statement of claim, Claimant aims with its infringement action at the following product families and at products that are technically essentially identical with regard to the features of the asserted claims of the patent-in-suit: 4 5 5. By written submission of 16 April 2025, without formally changing the wording of the requests submitted with the statement of claim, the Claimant applied for leave to amend the case so that the infringement action also covers the AM67x product. To this effect, Claimant submitted a redline version of an amended statement of claim the reasoning of which contains supplementary submissions on the AM67x product. After having heard the Defendants, which opposed, the judge-rapporteur postponed the decision on the application until after the forthcoming oral hearing, and, pending that decision, gave Defendants the opportunity to respond in writing in substance (cf. order of 14 May 2025) which they did on 11 June 2025 within the time period set. The amended statement of claim adds the following products to the list from the statement of claim as originally filed: 6 6. When arguing the infringement, in its statement of claim, Claimant refers exemplary to the AM62Ax SitaraTM, thereby alleging that the arguments apply in the same way to all other attacked embodiments. 7. A copy from Defendants’ webpage presenting the product AM62Ax SitaraTM is submitted as Exhibit C 6, a copy of the data sheet as Exhibit C 6a and a copy of pages 1 to 917 of the Technical Reference Manual as Exhibit C 6b. 8. The AM62Ax™ Sitara is equipped with a Cortex-A53 processor and a Generic Interrupt Controller GIC-500 of the company ARM. A copy of the Technical Manual for the Cortex-A- 53 processor and for the ARM GIC-500 is submitted as Exhibit C 7 and Exhibit C 7a respectively. A copy of the ARM Programmer’s Guide for ARMv8-A, which, according to Claimant, is a supplementary publication relating to the ARM Cortex-A processors is submitted as Exhibit C 7b. 9. In its statement of claim, with regard to the second group of Defendants’ products equipped with the Cortex-A72 processors, Claimant states that the two processors concerned are fully comparable with regard to all features relevant to the case. 10. By order of 1 April 2025, the judge-rapporteur rejected a request of the Claimant pursuant to R. 12.4, R. 36 RoP to allow filing a further written submission regarding arguments contained in the Defendants’ rejoinder in the infringement proceedings on the grounds of lacking substantiation. By order of 22 May 2025, the panel dismissed Claimant’s request for panel review pursuant to R. 333 RoP. 11. On 16 April 2025, in parallel to its afore-mentioned request pursuant to R. 333 RoP, the Claimant again applied to allow a further written submission regarding the Defendants’ arguments in the rejoinder in the infringement proceedings, this time with formally valid reasons. By order of 14 May 2025, the judge-rapporteur postponed the decision until after the forthcoming oral hearing with regard to the functionality AVS Class 0, and, pending that decision, gave first Claimant and then Defendants the opportunity to file a further written submission strictly restricted to that topic. Both sides used that opportunity and filed written submissions within the time limits set. In all other respects, the order of 14 May 2025 dismissed Claimant’s request. 7 REQUESTS OF THE PARTIES 12. Claimant requests: 1. Defendants are ordered to cease and desist from making (only Defendant 2) offering, placing on the market, using or importing or storing for these purposes (all Defendants) a multiprocessor system comprising: a first processor; a second processor coupled to the first processor by a first bus; a second bus coupled to the first bus; a clock gating unit directly coupled to the first processor and the second processor; a first and second peripheral device coupled to the second bus; and an intelligent interrupt distributor coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating unit, wherein the intelligent interrupt distributor is operable such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt bus to one of the first and the second processors which is in an idle state, and wherein the intelligent interrupt distributor adjusts an operating frequency and voltage of the first and the second processors by sending commands to the clock gating unit to maintain a throughput that is the same as that for an equivalent single processor system in Germany and France; 2. European Patent EP 2 746 957 has been infringed by making (Defendant 2), offering and placing on the market (all Defendants) multiprocessor system as described in no. 1 in the UPC member states Germany and France. 3. Defendants are ordered at their own expense • to recall the products referred to in no. 1 from the channels of commerce, • to definitely remove the products referred to in no. 1 from the channels of com- merce and • to destroy the products referred to in no. 1. 4. Defendants are ordered to inform the Claimant of • the origin and distribution channels of the infringing products, • the quantities produced, manufactured, delivered, received or ordered, as well as the price obtained for the infringing products; and • the identity of any third person involved in the production or distribution of the infringing products. 5. Any failure to comply with the orders pursuant to no. 1, 3 and 4 will render Defendants liable to pay to the Court a penalty of up to EUR 250,000 – in the case 8 of non-compliance with the injunction of up to EUR 250,000 per day of non- compliance. 6. The order to cease and desist is immediately enforceable. The other orders are enforceable only after Claimant has notified the Court which part of the orders it intends to enforce and the notification has been served on Defendants. 7. Defendants are liable for all damages resulting from the patent infringement described in no. 1. 8. Defendants are to bear the legal costs of the proceedings. 13. Defendants request: A. As a main request, I. to dismiss the infringement action in full; II. to order the Claimant to bear the costs. B. As an alternative request, for A.I, to dismiss the request for recall, removal and destruction as disproportionate (re- quests no. 3). C. As a further alternative request for A.I, to limit the measures for recall and removal to resellers or customers that have not yet implemented the accused chips in their products or started to introduce the implemented chips in their manufacturing process (requests no. 3, first two bullets). 14. In their submission of 11 June 2025 regarding the response in substance to the amendment to the statement of claim, Defendants, as a precaution measure in case of infringement being established, request the Court to order Claimant to provide an enforcement security, covering at least an amount equal to the value in dispute. 15. During the oral hearing, Claimant requested to include – on an auxiliary basis – a request to issue a permanent injunction for indirect infringement, Art. 63 (1), 26 UPCA, i.e. to order Defendants to cease and desist from supplying or offering and supply to third parties within the terri- tory of Germany and France multiprocessor system comprising: a first processor; a second processor coupled to the first processor by a first bus; a second bus coupled to the first bus; 9 a clock gating unit directly coupled to the first processor and the second processor; a first and second peripheral device coupled to the second bus; and an intelligent interrupt distributor coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second pe- ripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating unit, that are suitable and intended to be configured to distribute interrupts received by the intelligent interrupt distributor on the first or the second peripheral interrupt line via the interrupt bus to one of the first and the second processors which is in an idle state, wherein the intelligent interrupt distributor adjusts an operating frequency and voltage of the first and the second processors by sending commands to the clock gating unit to maintain a throughput that is the same as that for an equivalent single processor system COUNTERCLAIM FOR REVOCATION 16. With regard to their counterclaim for revocation (CC 51398/2024, UPC CFI 524/2025), Defendants request: The European patent EP 2 746 957 is revoked entirely with effect to the territory of France and Germany. 17. Claimant having filed an Application to amend the patent (App 62729/2024) requests: I. the Counterclaim for Revocation lodged at the registry on 12 September 2024 and serviced on Defendant of Counterclaim for Revocation on 24 September 2024 be dismissed. II. the patent in suit EP 2 746 957 B1 be maintained: 1) as granted; 2) in the alternative, based on one of the proposed amendments of the claims of the patent in suit EP 2 746 957 B1 (Auxiliary Requests 1 to 9 as filed on 25 November 2024); 3) further in the alternative and to the extent not reflected in one of the Auxil- iary Requests, in parts based on the independent validity of one or more of its dependent claims in combination with independent claim 1 as granted; and III. Defendants and Claimants of Counterclaim for Revocation are ordered to pay the costs of the proceedings. 18. With its brief of 3 March 2024 (containing the Rejoinder to the counterclaim for revocation and the Reply to the defence to the application to amend the patent), Claimant filed two additional auxiliary requests 6a and 8a. Defendants consider these auxiliary requests to be late and inadmissible (Rejoinder to the Application to amend the patent, p. 6). 10 19. In his order of 9 July 2025 that prepared the oral hearing, the judge-rapporteur informed Claimant that request II.3) cited above that pertains to Claimant’s application to amend the patent could be subject to concerns, considering the legal standards set out in LD Mannheim’s decision of 2 April 2025, UPC CFI 359/2023, Fuji v. Kodak et al., paras. 159 et seqq. POINTS AT ISSUE 20. The parties are in dispute about different aspects of the case at hand. ENTITLEMENT 21. Defendants dispute that the patent-in-suit and the asserted claims arising from past use were validly assigned to Claimant. INFRINGEMENT 22. Defendants dispute that the attacked embodiments realize claim 1 of the patent. They state that the attacked embodiments as shipped do not implement a possibility to adjust voltage during operation, in particular not in Standby Mode, WFI Mode and in Operation Performance Points OPP adjustments. According to Defendants, the attacked embodi- ments do not implement Dynamic Voltage and Frequency Scaling (DVFS). The exemplary AM62Ax could be configured by the customer to run the processor at one of two different voltage levels that remains constant during operation. Therefore, it used OPPs with fixed voltages during operation. According to Defendants, the attacked embodiments do not provide for an even distribution of the interrupts across the processors which would be counter to feature 7, 8. 23. Defendants further state that the GIC-500, being considered as the Intelligent Interrupt Distributor, cannot change the operating frequency (and voltage) by sending a command to a Clock Gating Unit (feature 8), in particular not for wake-up from WFI state and not for OPP selection. 24. Defendants argue that AVS is not a technique for dynamic power saving in accordance with feature 8, rather a technique that allows a manufacturer to compensate for performance differences between individual units of the same product model caused by natural varia- bility in the manufacturing process. 11 25. Defendants further dispute that the attacked embodiments involve a direct coupling be- tween the GIC-500 and a Clock Gating Unit (feature 6.4). 26. Defendants point out that the attacked embodiments are not produced in France or Ger- many. According to Defendants, neither Defendant 2 nor Defendant 3 were involved in the manufacturing of the attacked products, and that Defendant 2 did not sell or distribute the attacked products while Defendant 3 did not store products, including the attacked prod- ucts. 27. For further details, reference is made the parties’ briefs and exhibits. COUNTERCLAIM FOR REVOCATION 28. Defendants base their identical counterclaims for revocation on the following ground of Art. 138 EPC in conjunction with Art. 65 (2) UPCA: - lack of inventive step (Art. 138(1)a) in conjunction with Art. 56 EPC). 29. Defendants argue that the subject-matter of claim 1 lacks inventive step - over a) the text book Preeti Ranjan Panda et al., “Power-efficient System Design”, ISBN 978-1-4419-6387-1, Springer Verlag, 2010, pages i-x, 1-54 and 249-253 (exhibit D CC 1 / Panda, “Panda”, extract of exhibit D CC 1a / Panda (full)) or b) the paper Junseob Lee and Nam Sung Kim, “Optimizing Total Power of Many- Core Processors Considering Voltage Scaling and Process Variations”, Proceed- ings of the 2009 ACM/IEEE international symposium on Low power electronics and design (ISLPED`09), pages 201-206, 19-21 August 2009 (exhibit D CC 2a / Lee, “Lee paper”) and the presentation Junseob Lee and Nam Sung Kim, “Op- timizing Total Power of Many-Core Processors Considering Voltage Scaling and Process Variations”, 9 October 2009, retrieved on 22 June 2024 from Internet address: http://ece752.ece.wisc.edu/Lee Kim slides 2009 (exhibit D CC 2b / Lee, “ Lee slides”) (together referred to as “Lee”), considered together as con- stituting a single source of disclosure, in view of common general knowledge, 12 - in addition over US 8,260,996 B2 (exhibit D CC 4 / Wolfe, “Wolfe”, US’996) in view of a) Panda (exhibit D CC 1); or b) Lee (exhibit D CC 2a/b); or c) the presentation C. Belleudy “Architecture multiprocesseur et faible conom- mation (partie 1)”, retrieved on 22 June 2024 from Internet address: http://ecofac2010.irisa.fr/cours-belleudy.pdf (exhibit D CC 6 / Belleudy, Eng- lish translation submitted in exhibit D CC 6a / Belleudy, “Belleudy”); - in addition over the textbook Kunio Uchiyama et al., "Heterogeneous Multicore Processor Technologies for Embedded Systems", ISBN 978-1-4614-0283-1, Springer Verlag, 2012, pages i-xi, 123-151 and 219-224 (exhibit D CC 5 / Uchiyama, “Uchiyama”) and the paper Huong Thien Hoang et al., “Design and Performance Evaluation of an 8-processor 8,640 MIPS SoC with Overhead Reduction of Interrupt Handling in a Multi-core System”, Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 193-196, 3-5 November 2008 (exhibit D CC 5a / Hoang, “Hoang”), considered together as constituting a single source of disclosure, in view of a) Panda (exhibit D CC 1); or b) Lee (exhibit D CC 2a/b); or c) Belleudy (exhibit D CC 6); - in addition over general/basic knowledge of the skilled person. 30. The Claimant in particular contends that neither the cited prior art nor the common general knowledge teaches or suggests to the skilled person the claimed ‘intelligent interrupt distributor’. For further details, reference is made to the parties’ briefs and exhibits. REASONS FOR THE DECISION 31. Both the infringement action and the counterclaim for revocation are admissible but unfounded. 13 A. ADMISSIBILITY 32. The international jurisdiction of the UPC finds its basis in Art. 31 UPCA, Art. 71b (1), Art. 4 (1) Brussels Ia Reg. with regard to Defendants 2 and 3 domiciled in Germany and in Art. 31, 71b (2), Art. 7 (2) UPCA with regard to Defendant 1 domiciled in the USA. The question as to whether Defendant 1 actually infringes upon the patent-in-suit in Germany and France relates to the merits of the case only (cf. Court of Appeal, order of 3 September 2024, UPC CoA 188/2024, GRUR 2025, 101, paras. 12, 13, 18). 33. The competence of the Local Division Mannheim follows from Art. 33 (1) (b) UPC with re- gard to the Defendants 2 and 3 and from Art. 33 (1) (a) UPCA with regard to the Defend- ant 1. Again, the question as to whether Defendant 1 actually infringes upon the patent-in- suit in Germany relates to the merits of the case only (cf. Court of Appeal, order of 3 Sep- tember 2024, UPC CoA 188/2024, GRUR 2025, 101, para. 18 (on Art. 7 (2) Brussels Ia Reg.)). As confirmed by Art. 33 (2) UPCA, with regard to territorial scope, the competence established under Art. 33 (1) (a) UPCA extends to all national parts of the same European patent in the UPC member states so that the Local Division Mannheim is also competent to hear the infringement action against Defendant 1 in relation to France. 34. Apart from that, international jurisdiction and internal competence also follow from Art. 31 UPCA, Art. 71b (1), (2), Art. 26 Brussels Ia Reg. and R. 19.7 RoP respectively as the Defendants did not raise objections and entered into appearance within the meaning of Art. 26 Brussels Ia Reg. before the court. 35. Claimant is entitled to bring the present action before the court, Art. 47 (1) UPCA. At least in cases like the present one in which the claimant is registered as owner of the patent-in- suit (exhibit C2), the question as to whether the claimant is the actual owner of the patent- in-suit relates to the merits of the case only. Otherwise, the defendant who has successfully disputed the actual ownership would not be protected by substantive res judicata from being sued again by the same claimant who seeks a second chance by presenting new evidence or better arguments without any change in the factual situation. 14 B. SCOPE AND ADMISSIBILITY OF THE REQUESTS I. Scope of the statement of claim 36. The reasoning of the statement of claim makes it unambiguously clear, that, in addition to the product families expressly named therein, the infringement action is also directed against such products that are technically essentially identical with regard to the features of the asserted claims of the patent-in-suit (cf. SoC, para. 33). 37. It also follows from the reasoning that Claimant wants the court to establish infringement for each of the products expressly named in its statement of claim. Claimant stated that all these products are designed and function in the same way in terms of the features of the asserted patent claims (cf. SoC, para. 35), thereby aiming at the goal that any factual deviation in this regard has to be clarified in the infringement proceedings at hand to the effect that, if the infringement action were successful, any later objection by Defendants that a specific product among those listed in the statement of claim is designed or functions differently in terms of the relevant features of the patent-in-suit would be excluded. II. Admissibility of introducing the AM67x product by Claimant’s brief of 16 April 2025 (App 18494/2025) 38. The amendment of the infringement case by introducing the AM67x product is permitted. 39. An amendment of a case within the meaning of R. 263 RoP occurs when the nature or scope of the dispute changes (cf. Court of Appeal, order of 21 November 2024, UPC CoA 456/2024, OrthoApnea et al). 40. The AM67x product is also based on an ARM Cortex-A53 processor and contains a GIC-500. Claimant states that AM67x operates in the same way as the other attacked embodiments, but believes to have found further evidence for AM67x being able to be run at different voltages and to adjust the operating voltage during operation. 41. Since it is undisputed that – besides the new evidence – the AM67x product has no characteristics relevant to the alleged infringement and different from the other attacked embodiment, the substantive scope of the asserted claims is in principle not extended beyond what was claimed in the statement of claim. As discussed above, the statement of claim covers all embodiments that have the same characteristics in terms of the features 15 of the asserted patent claim as the products listed in the statement of claim. If the infringement action in the substantive scope of the statement of claim were successful, the AM67x product would also be covered. However, expressly introducing the AM67x product does extend the substantive scope beyond the statement of claim to the effect that it is already bindingly established in the proceedings at hand that the AM67x does not differ from the other attacked products with regard to the relevant features of the patent claim. In consequence, the introduction of AM67x product constitutes an amendment within the meaning of R. 263 RoP. 42. The amendment is not excluded under R. 263.2 RoP. 43. The panel is convinced that Claimant was not negligent by not introducing the AM67x product at an earlier stage but only after the rejoinder in the infringement action was filed (R. 263.2 (a) RoP). Even if the product overview (exhibit C 17), as Defendants state, was already published in April 2024, the AM67x SDK User Guide (exhibit C 15) was published only in December 2024 and Defendants did not specifically state an earlier release date for the AM67x product on the relevant markets in France and Germany than December 2024 either. Against this backdrop, it is irrelevant that Claimant does not base its amendment on the AM67a SDK User Guide (exhibit C 15) but on the product overview (exhibit C 17) and on its general statement that, moreover, the AM67x product has the same relevant characteristics as the other attacked products. The fact that Claimant, according to its own statements, came across the offering of the AM67x product in Germany only in February 2025 when analyzing Defendants’ rejoinder in the infringement action and filed the application to amend the case only on 16 April 2025, does not yield another result. While in particular the time period of two month between the discovery of the offering and the filing of the application may be critical depending on the circumstances of the individual case, the panel does not yet consider the waiting time to be detrimental on the instant facts of the present case, given that Claimant had not only to analyse the AM67x product and gather information about it, but had also to analyse the rejoinder in the infringement action and the reply in the counterclaim for revocation as to whether their content is decisively detrimental to Claimant’s case. 44. The amendment does not unreasonably hinder the Defendants in the conduct of their actions (R. 263.2 (b) RoP). The AM67x product is essentially the same as the other attacked products with regard to the characteristics relevant to infringement. The Defendants, as 16 owners of the AM67x product’s design and technical information, were fully aware of the relevant evidence and functionality. As discussed below, the further evidence and functionality in the context of the AM67x product do not constitute infringement either. No significant additional effort is required to assess the case with regard to the AM67x product. Thus, it can be left open whether the result would otherwise be different. 45. Taking the circumstances into account, when balancing the interests involved, the panel exercises its discretion to allow the amendment. The infringement action is ready for a decision also with regard to the AM67x product. No significant additional effort is caused by also assessing this product, thereby avoiding a possible separate legal dispute as to whether this product differs decisively from the other attacked products so that it is not covered by the res iudicata effect but calls for a different legal outcome. III. Amendment from the oral hearing 46. In contrast, the panel decides not to allow the amendment introduced in the course of the oral hearing. 47. That amendment constitutes an amendment within the meaning of R. 263 RoP. The transition from direct to indirect infringement changes the nature of the case even if both infringement arguments are based on the same products because the requirements for as well as the legal consequences of direct and indirect infringement differ significantly. In the case of Art. 25 (a) UPCA in which the product implements all features of the patent claim, the offering and placing on the market in principle suffices to establish infringement, whereas in the case in which the product does not implement all features, further circumstances are required to constitute an indirect infringement within the meaning of Art. 26 UPCA in terms of offering or supplying. Furthermore, the types of possible infringing acts within the meaning of Art. 25 (a) UPCA go beyond offering and placing on the market. The legal consequences of an established infringement in principle also differ, e.g. with regard to the substantive scope of injunctive relief. 48. The amendment at hand is excluded under R. 263.2 RoP. Claimant did not sufficiently explain why it was not able to bring forward an indirect infringement argument as an auxiliary request at an earlier stage of the proceedings. Therefore, the panel is not convinced that Claimant applied reasonable diligence (R. 263.2 (a) RoP). Moreover, the 17 amendment unreasonably hinders Defendants in the conduct of their actions (R. 263.2 (b) RoP). It cannot be expected from Defendants to defend themselves against an assertion of indirect infringement when raised in the oral hearing for the first time on the spot - circumstances that exceptionally would yield another result are not demonstrated nor are they apparent. The statement that AM62Ax product, including the ARM cortex-53 processor, could at least be configured by the customers to perform DVFS without any amendment to the requests (Reply, para. 43), is not sufficient to be interpreted as amendment of the case to the effect that it encompasses indirect infringement. The same applies to the (more detailed) statements in the brief of 28 May 2025 that, in addition, are not permissible (cf. infra). 49. For reason given above, even if the foregoing circumstances were not to constitute an exclusion under R. 263.2 RoP, the panel exercises its discretion not to allow the amendment, taking into account the circumstances of the individual case, the interests involved and the right to defence. On a regular basis, a defendant cannot reasonably be expected to defend himself against the assertion of an indirect infringement that has been raised in the oral hearing for the first time on the spot. Circumstances pointing to another result are not apparent. This is even more true as Claimant had based its allegation of infringement repeatedly on new aspects. C. SUBSTANTIVE SCOPE OF THE PATENT-IN-SUIT 50. The patent-in-suit relates to an intelligent interrupt distributor. 51. According to the patent specification, computing systems such as desktop computers and mainframes are typically designed to provide the highest possible throughput. However, against the backdrop of the proliferation of mobile computing systems such as laptops, smartphones and tablets, the focus shifted towards optimizing both speed and battery lifetime to minimise their power consumption. In this context, the description of the patent-in-suit explains that the microprocessor or microcontroller typically gathers information from various sources to make decisions or measurements. Most of that information would reach the microprocessor via an interrupt. According to the patent-in- suit, various techniques at both the architecture and circuit level have been investigated to maximize throughput and minimise latency of the computing system. These techniques typically lead to an increase in the total power dissipation of the system. In order to 18 compensate for the increased power dissipation, techniques had been introduced to reduce system power consumption such as body biasing and clock gating, for example. The patent-in-suit further explains that the performance of general purpose microcontroller or microprocessor systems is typically limited by the number of interrupts that need to be handled simultaneously. According to the patent-in-suit, the design of these microcontroller systems typically requires a certain throughput to be able to handle the required number of simultaneous interrupts. To maintain adequate throughput would require a minimum supply voltage to be provided to the microcontroller system which then determines the power consumption of the microcontroller system (cf. paras. [0001] to [0003]). 52. The description of the patent-in-suit does not expressly formulate the technical problem to be solved. However, the objective technical problem is to provide a multiprocessor system that allows for reducing power consumption without affecting throughput when handling interrupts. 53. As a solution, the patent-in-suit proposes in claim 1 a microprocessor system, the features of which can be structured as follows: A multiprocessor system (300) comprising: 1. a first processor (310); 2. a second processor (320) coupled to the first processor by a first bus (340); 3. a second bus (345) coupled to the first bus (340); 4. a clock gating unit (390) directly coupled to the first processor and the second processor; 5. a first and second peripheral device (354,355) coupled to the second bus; and 6. an intelligent interrupt distributor (350) 6.1 coupled to the first bus and 6.2 directly coupled to the first and second processor by an interrupt bus (315) and 6.3 directly coupled to the first and second peripheral device by a first and sec- ond peripheral interrupt line and 6.4 directly coupled to the clock gating unit, 19 7. wherein the intelligent interrupt distributor is operable such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt bus to one of the first and the second processors which is in an idle state, and 8. wherein the intelligent interrupt distributor adjusts an operating frequency and voltage of the first and the second processors by sending commands to the clock gating unit to maintain a throughput that is the same as that for an equivalent single processor system. 54. Some features require further explanation. Interrupt 55. An interrupt within the meaning of the patent-in-suit has to be distinguished from a task (or process or thread). 56. The person skilled in the art is an electrical engineer with experience in electrical digital data processing system architecture. 57. According to his/her common general knowledge, the skilled person understands an inter- rupt to be different from a task (or process or thread) both in terms of concept and require- ments for handling. 58. According to this understanding, an interrupt operates at a kernel mode, thus having the highest priority. An interrupt is a signal that temporarily halts the normal execution of the processor in order to address an urgent event. When triggered, it causes the processor to stop its current activity, save its state, and jump to an Interrupt Service Routine (ISR). In- terrupts are typically used to handle events such as inputs from a keyboard or mouse, hard- ware failures, and I/O operations. In principle, their execution cannot be fragmented, in particular not be paused and resumed later. 59. In contrast, a task (also known as a process or thread) is a program or part of a program that the operating system schedules for execution. Each task has a full execution context: memory space, registers, program counter... Tasks are the main units of work scheduled and executed by the Operating System (OS). Tasks maintain their own context, allowing them to be paused and resumed at any point. 60. Unlike tasks, interrupts do not have their own execution context. They borrow the context of the interrupted task and typically run in kernel or privileged mode. 20 61. Interrupts are short-lived and should be executed quickly (to handle events and return con- trol back to the interrupted task). In contrast, tasks can run for long periods and may be interrupted, suspended, or terminated. 62. Therefore, interrupts are asynchronous and priority-based, rather than being scheduled by the OS in the same way as tasks. Tasks are managed by the OS scheduler, which determines which task runs at any given time based on policies like priority or time-slicing. 63. The patent specification of the patent-in-suit, which is its own lexicon and may therefore use a certain terminology in the context of the patent as defined therein, does not point to a different understanding. By explaining that most of the information gathered reaches the microprocessor via an interrupt (para. [0002]) that comes via a peripheral interrupt line (para. [0009], cf. also feature 7 and para. [0011]) and by pointing out that several interrupts may need to be handled simultaneously (para. [0003]), the patent description underpins that the execution of an interrupt is not scheduled by an operating system and that an interrupt is, as already reflected in its name, typically urgent so that it needs priority exe- cution and cannot be postponed or paused for (further) execution at a significantly later point in time. Therefore, the interrupt within the meaning of the patent-in-suit also has priority over other workload of the processor, the execution of which is interrupted and postponed in the event of the occurrence of an interrupt. The fact that an interrupt is exe- cuted without interruption or otherwise pausing is confirmed by Fig. 5 to 7 which show that each interrupt is executed completely, and without any interruption before the same core starts the execution of the next interrupt. Finally, the execution of an interrupt is not sched- uled by the operating system but merely arrives at the processor via an interrupt line (so in the prior art, Fig. 2, para. [0009]) or, according the invention, arrives at and is gathered by the intelligent interrupt distributer IID and is then distributed to a certain processor by the intelligent interrupt distributer IID based on their availability and, as the case may be, on a priority predefined by the programmer, but without a scheduling instance at OS level (cf. paras. [0007], [0010], Fig. 3). 64. Against this backdrop, contrary to Defendants, the brackets in para. [0018] do not imply that every workload constitutes an interrupt within the meaning of the patent-in-suit, but merely indicate that interrupts constitute a workload for the processor. 21 65. According to the patent-in-suit, the operations to be processed for and associated with an interrupt are named interrupt service routines (ISR) or interrupt handlers (cf. para. [0013] line 38). (Interrupt) bus 66. A bus within the meaning of the patent-in-suit is a device that communicates data between components. In contrast to a line it is not a dedicated point-to-point connection between two components (cf. e.g. para. [0009] mentioning buses and lines in this regard). Rather, it connects several components that can communicate with each via the bus using e.g. ad- dresses. 67. An interrupt bus is a bus serving the purpose of transferring interrupts from the Intelligent Interrupt Distributor IID to the processors (para. [0010]). However, claim 1 does not ex- clude that an interrupt bus is also used for other communication. Clock gating unit 68. As already reflected in its name, the clock gating unit must be able to gate the clock, i.e. to block the clock signal. This is confirmed by the description that expressly mentions clock gating as a technique to reduce power consumption (cf. para. [0002] at the end). The clock gating unit may, e.g., be part of a Clock Generation Unit (CGU) 390 that, besides generating the clock signal (para. [0009]), may also provide dynamic clock gating and scaling for the multiprocessor system 300, i.e. adjustments of the clock frequency for (certain) processors (cf. para. [0010] “Clock Generation Unit (CGU) 390 provides dynamic clock gating and scal- ing for multiprocessor system 300 … […] … IID 350 sends commands to CGU 390 to adjust the clock (frequency) for processor 310 and 320”). 69. It follows from feature 8 in conjunction with the aforementioned para. [0010] of the de- scription that a clock gating unit in accordance with claim 1 is also involved in the execution of adjustments of the frequency. 70. In consequence, neither a unit that only blocks the clock signal without being involved in the adjustment of its frequency nor a unit that only adjusts the frequency without being able to entirely block the signal is a clock gating unit in accordance with claim 1. 22 71. Even if it is not decisive in the case at hand, the clock gating unit is not just a functionality but a hardware unit within the microprocessor system because, when transferring from the single-processor system (para. [0009]) to the multiple-processor system, the hardware and its connections change (cf. para. [0010] et seqq., in particular [0012]). Intelligent Interrupt Distributor (IID) (features 6 to 8) 72. According to feature 7, the intelligent interrupt distributor (“IID”) is operable such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt bus to one of the first and the second processors which is in an idle state, wherein (feature 8) the intelligent interrupt distributor adjusts an operating frequency and voltage of the first and the second processors by sending commands to the clock gating unit to maintain a throughput that is the same as that for an equivalent single processor system. Distribution of interrupts (feature 7) 73. The IID has the first function of distributing the interrupts to the processors, thereby being able to distribute, via the interrupt bus, an interrupt received on the first or second periph- eral interrupt line to one of the first and the second processors which is in idle state (fea- ture 7). 74. While the IID may in some modes also be able to distribute interrupts to busy processors instead of an idle one, the feature recites that the IID must be able to distribute the inter- rupt to the one of the processors which is in idle state. This implies that the IID is able to obtain, in an unspecified manner, information about the workload of the processors and to decide to send the interrupt to the idle processor. This understanding is confirmed by the patent description (cf. “an Intelligent Interrupt Distributor (IID) is provided … in accord- ance with the invention to balance interrupts among the processors” (para. [0005]); “Herein is described an intelligent interrupt distributor for balancing interrupts (workload) in a highly parallelized system” (para. [0018]); relating to embodiments: “If the processor is in idle mode and not busy then the IID schedules the incoming interrupt to that proces- sor. […] The IID … distributes the interrupts among the multiple processors based on avail- ability” (para. [0007]); “IID 350 schedules interrupts between processors 310 and 320 by examining the workload of processors 310 and 320. If processor 310 or 320 is free, the coming interrupt is scheduled for the free processor” (para. [0012]); “IID 450 routes the 23 interrupt to the first available processor … […] IID 450 checks return from interrupt signal 314 to identify which processor, processor 480 or processor 485 is free or idle” (para. [0013]); “Because interrupt 502 is completed after 3 seconds, the next interrupt, interrupt 503 is sent to processor 320 by IID 350 because processor 310 is still busy” (para. [0015])). 75. The meaning of idle state in this context does not refer to any predefined operating mode which needs special wake-up procedures to activate the processor. Rather, idle state in this context simply means that the processor is not busy so that it has capacity to execute an interrupt (cf. para. [0007], para. [0013] (line 42: “free or idle”)). There are no pointers to the opposite in the patent description. Adjustment of frequency and voltage (feature 8) 76. The IDD has the second function of adjusting an operating frequency and voltage of the first and second processor by sending commands to the clock gating unit (feature 8). In accordance with the claim’s wording, the IID must be able to adjust frequency and voltage for both the first and the second processor (cf. also para. [0007] at the end). By reducing frequency and voltage for both processors, the power consumption is reduced while the throughput of a single processor system is maintained despite reducing the frequency which allows for reducing voltage in accordance with the lower frequency (cf. para. [0005] lines 35-36; paras. [0007], [0008]). It is therefore not sufficient if the IID were only able to make the adjustment just for one of the processors, without implying that it is able, in every case, to simultaneously adjust frequency and voltage for both processors (see para. [0018]). 77. This function further implies that the IID is in control of the adjustment because it is the IID that adjusts frequency and voltage in accordance with feature 8 and that sends a command to the clock gating unit in this context. The capability to distribute the interrupts and to adjust frequency and voltage in accordance with feature 7 and 8 constitutes the intelli- gence of the IID that is already reflected in its name. The mere execution of the adjustment commanded by the IID can be left to other entities. 78. Since an adjustment of frequency alone is not sufficient to make it possible to reduce power consumption while maintaining the throughput in accordance with feature 8 (cf. Fig. 1, 24 para. [0008]; para. [0018]), the IID must be able to adjust the voltage alongside and in ac- cordance with the frequency. This is confirmed by para. [0005] which in general addresses the appropriate management of both frequency and voltage according to the invention (cf. “… by appropriately managing the computer system’s operating voltage and frequency… […] However, the voltage and frequency may be appropriately reduced so that throughput remains the same as in the single processor configuration”; emphasizes added). In accord- ance with the invention, the task of managing both frequency and voltage is assigned to the IID as shown in feature 8 and throughout the patent description (cf. para. [0007] (“The IID incorporates both static and dynamic tuning of the computer system voltage and fre- quency. […] In summary, the IID detects the interrupts from the peripheral devices, distrib- utes the interrupts to the processors and adjusts the supply voltage going to the processors and adjusts the operating frequency of the processors”), para. [0010] (“Based on the inter- rupts received, IID 350 adjusts both the frequency and the voltage”), para. [0018] (“The intelligent interrupt distributor may distribute the interrupts between the processor cores. This may allow lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced”). The voltage required for a certain throughput (and thus for a certain frequency) determines the power consumption of the microcontroller system (para. [0003] at the end). 79. The adjustment must be possible during the operation of the processor system. This fol- lows from the structure of claim 1 because the distribution of the interrupt and, in this context (“wherein”), the adjustment of frequency and voltage in accordance with feature 8 are executed upon the receipt of an interrupt (feature 7 “operable such that an interrupt received on the first or the second peripheral interrupt line is distributed … (feature 8) wherein …”). The passages in the patent description cited under para. 63 supra that relate to the distribution of interrupts also underpin that the adjustment takes place during op- eration and in the context of the reception of an interrupt to be distributed. The same follows from Fig. 5 to Fig. 7 in conjunction with paras. [0014] et seqq., which explain the adjustment during operation in order to handle interrupts. According to sub-claim 9, it is only an additional feature of the claimed multiprocessor system that the IID is configured to also statically tune the operating frequency and voltage of the multiprocessor system (cf. the special embodiment described in para. [0007]: “The IID incorporates both static and dynamic tuning of the computer system voltage and frequency.”) 25 80. Operating frequency and voltage must be adjusted in such way that a throughput is main- tained that is the same as that for an equivalent single processor system. As reflected inter alia in para. [0003] last sentence and in para. [0005] second to last sentence, a certain fre- quency corresponds to a certain minimum voltage. The indication of purpose (“to main- tain”) contained in feature 8 relates to the effect of the adjustment of the operating fre- quency and voltage. This follows unambiguously from the description (cf., e.g., para. [0005] last but one sentence, para. [0016] in conjunction with Fig. 7, para. [0018]). The purpose implies that the IID must be able to adjust operating frequency and voltage to the effect that a throughput is maintained that is the same as that for an equivalent single processor system. 81. In this context, the IID must be able to positively adjust frequency and voltage to the effect foreseen in feature 8. Just keeping frequency and voltage the same and putting the second processor to work to avoid using the first processor at higher frequency and voltage is not sufficient. This implies that the capability to adjust frequency and voltage must in particular encompass the capability to reduce frequency and voltage in a way that, by using more than one processor at lower frequency and voltage, maintains a throughput that is the same as that for an equivalent single processor system that operates at a non-reduced fre- quency and voltage level (cf. para. [0005] second to last sentence). Otherwise, the capabil- ity to operate in accordance with the embodiment described in para. [0016] and Fig. 7 where frequency and voltage are dynamically reduced would not be a prerequisite of an IID – despite the fact of being described to be in accordance of the invention and the ab- sence of any pointer to opposite. In consequence, a microprocessor system with more than one processor that, by using a second processor to process interrupts as well, allows for just statically reducing frequency and voltage compared to a single processor system with the same throughput is not sufficient to implement the teaching of claim 1. It is not suffi- cient either, if an interrupt distributor merely were distributing the interrupts across the processors (including idle ones) and a separate functional unit that is in general in charge of power management in response to processor workload were reducing operating fre- quency and voltage in accordance with the workload of the processors. 82. The fact that feature 8 speaks more generally of adjusting instead of reducing yields no deviating result. Rather, the IID must be able to generally adjust frequency and voltage whereas this adjustment must encompass the possibility to reduce frequency and voltage 26 in accordance with feature 8 and the embodiment described in para. [0016] and Fig. 7. The capability to generally adjust frequency and voltage allows for the flexibility to opt between maximum throughput mode and minimum power mode, an option that is in accordance with the invention (cf. para. [0005] last sentence). Also, the skilled person immediately and undoubtedly understands that cases can occur in which frequency and voltage, having been reduced to minimise power consumption, must be increased again to maintain the same throughput of an equivalent single processor system. For example, if the ideal situa- tion shown in Fig. 5 (where the pair of odd-numbered interrupts has the same execution time of the pair of even-numbered interrupts) is altered by swapping the times of receipt of Interrupts 3 and 4, then in Fig. 7 the first core 310 would need to operate at higher frequency and voltage (at least while executing Interrupt 3) in order to complete the exe- cution of both Interrupts 1 and 3 within the overall execution time of 12 seconds, which is the overall execution time of the equivalent single processor system. Even in that scenario, the overall power consumption would still be lower than that of the single-processor sys- tem, in accordance with the teaching of the patent-in-suit. 83. The adjustment must be made by means of sending commands to the clock gating unit. In this regard, the claim leaves the content of the command open. Therefore, it suffices that, e.g., the command to the clock gating unit results in an adjustment of the frequency in accordance with feature 8 whereas the adjustment of the voltage is commanded by other means and executed by another entity than the clock gating unit. Operable (features 7 and 8) 84. The term operable means that the IID is enabled to operate in a way that is described in feature 7 and 8. Therefore, the IID must be able without further ado to dynamically adjust both operating frequency and voltage during operation (and to distribute the interrupts). Furthermore, the adjustment must encompass an adjustment mode that results in main- taining a throughput that is the same as that for an equivalent single processor system in accordance with feature 8. In consequence, the IID as implemented must already be able to operate as foreseen in features 7 and 8. This means that all the routines have to be already implemented that allow for the IID operating in accordance with feature 7 and 8. 85. On the other hand, it is not necessary that the IID always opts to operate in the way of feature 7 and 8. The patent-in-suit does not exclude that the IID may also operate e.g. to 27 increase the throughput by maintaining or increasing operating frequency and voltage and operating all processors at this working point instead of reducing the power consumption (cf. para. [0005] and para. [0018] (“may”)). The only decisive factor is that the IID is able to adjust frequency and voltage in accordance with feature 7 and 8 as outlined supra when distributing incoming interrupts. First and second processor; first and second peripheral device; first and second bus 86. By numbering the elements mentioned above, also considering the use of the term “com- prising”, claim 1 does not exclude a design that involves more than two processors, periph- eral devices and buses as long as at least two of them are connected and work together with each other and the other elements as foreseen in claim 1. Similarly, claim 1 does not exclude more than one (intelligent) interrupt distributor and more than one clock gating unit as long as at least one interrupt distributor and at least on clock gating unit exist that fulfill the relevant features 4, 6, 8 and 7, respectively and are connected and work together with each other and the other elements as foreseen in claim 1. Directly coupled (features 4, 6.2, 6.3 and 6.4) 87. The term “directly coupled” (features 4, 6.2, 6.3 and 6.4), in contrast to the term “coupled” without further specification which also involves indirect coupling, means that the ele- ments are coupled without any intermediary functional unit other than a non-functional interconnection such as buses or lines. It does not establish any restriction as to the means of coupling. In particular, the term “directly coupled” does not call for a point-to-point con- nection or other connection specifically dedicated to the coupling partners. 88. This already follows from the wording and structure of claim 1 that distinguishes between the type of coupling – restricted to direct coupling (cf. features 4, 6.2, 6.3 and 6.4) or not restricted in this regard (cf. features 2, 3, 5, 6.1) – and the means of coupling that are, if any restriction exists in this regard, specified by the term “coupled by” (cf. features 6.2 and 6.3). In contrast, the simple term “coupled to” only specifies the coupling partner without establishing any restriction as to the type or means of coupling. 89. This understanding is confirmed by the patent description (cf. distinction between con- nected and directly connected in Fig. 2 in conjunction with para. [0009] and in Fig. 3 in conjunction with paras. [0010] and [0011]). While, in the prior art, the external devices such 28 as the Analog-to-Digital-Converter ADC are directly coupled to the processor by Peripheral interrupt lines 285 and therefore send interrupts directly to the processor (cf. Fig. 2, para. [0009]), according to the invention, ADCs are not directly coupled to the cores but con- nected via the IID as intermediary unit with a function that goes beyond connecting (cf. Fig. 4, para. [0013] “ … the relevant ADC, ADC 420 or ADC 425 sends an interrupt on pe- ripheral interrupt 475 or 476, respectively, to either processor 480 or processor 485 which is intercepted by IID 450. IID 450 routes the interrupt to the first available processor …” (emphasis added); Fig. 3, para [0011] “Note, that unlike in FIG. 2, all peripheral interrupt lines 370, 375, 380 and 385 directly connect to IID 350 and not to cores 310, 320”). D. COUNTERCLAIM FOR REVOCATION 90. The counterclaim, being directed against the French and the German part of the patent-in- suit, is to be dismissed. The subject-matter of claim 1 involves an inventive step over the prior art presented in the proceedings at hand. 91. The Defendants divide the features of claim 1 in a subset containing features 1 to 7 and being named “basic structural and functional configuration” (hereinafter referred to as “basic configuration”) and a further subset containing only feature 8 and being named “basic idea or core concept”. For ease of reference only, the term “basic configuration” will be used in the aforementioned meaning. I. Legal framework 92. According to Art. 56 EPC, an invention shall be considered as involving an inventive step if, having regard to the state of art, it is not obvious to a person skilled in the art. 93. The suitable starting point for the assessment of inventive step is not limited to the closest prior art. Since there may be several ways to arrive at a conclusion, there may accordingly exist several starting points. The decisive point is rather whether such starting point con- stitutes a suitable starting point which the relevant person skilled in the art would take into account, if confronted with the problem to be solved (cf. Central Division Munich Section, decision of 16 July 2024, UPC CFI 14/2023 mn. 8.6; Central Division Paris Seat, decision of 21 January 2025, UPC CFI 311/2023 mn. 57). In this regard, on a regular basis, a solution as claimed is obvious, if, starting from a suitable starting point in the prior art, the skilled person would be motivated (i.e., have an incentive) to consider the solution and implement 29 it as a next step (cf. Central Division Munich Section, decision of 16 July 2024, UPC CFI 14/2023 mn. 8.6). 94. Contrary to Claimant, depending on the circumstances of the individual case, a textbook or other scientific publication may be a suitable starting point for the person skilled in the art when confronted with the objective problem of the invention that is to be solved. II. Skilled person 95. As mentioned above, the relevant skilled person in the case at hand is an electrical engineer with experience in electrical digital data processing system architecture. Being a distin- guished professor with meaningful practical experience and, respectively, a technical advi- sor with meaningful academic background who, in addition, is the inventor of many patents in the relevant field, both private experts of the parties have knowledge and skills that go far beyond the level of the relevant skilled person. III. Lack of inventive step over any asserted combination encompassing Panda (exhibit D CC 1) Disclosure of Panda 96. The Defendants invoke Panda for feature 8 (labelled “basic idea or core concept”) and, in their reply to the defence to the counterclaim for revocation (Reply-CCR), for feature 8 including an IID (feature 6) and a clock gating unit (feature 4). However, Panda fails to di- rectly and unambiguously disclose any of these features. 97. The Defendants in particular refer to Fig. 3.7 which is depicted infra alongside a copy thereof annotated by Defendants (cf. Reply-CCR, para. 61): 30 98. Fig. 3.7 is part of Panda’s Chapter 3 “Power-efficient Processor Architecture”, sub-chapter 3.1 “introduction”, sub-sub-chapter 3.1.1 “Power Budget: A major Design Constraint”, sub- sub-sub-chapter 3.1.1.1 “Why does Parallel Processing Reduce Power?”. This already indi- cates that the chapter deals with processor architecture alone and not with how to operate a certain processor architecture that involves more than one processor. 99. Chapter 3.1.1.1. with Fig. 3.7 discloses the relationship between power (consumption) on one side and voltage and clock frequency on the other side, wherein the relationship is quadratic with regard to voltage and linear with regard to frequency (cf. Panda, formula in Fig. 3.7 and on p. 45). In this context, in line with the topic of chapter 3 relating to processor architectures, Fig. 3.7 compares, in terms of processing a single task A, a system 1 that contains one processor with processing the same task A within the same time budget T 31 using a system 2 with two processors. It further discloses that, in accordance with the given formula, processing task A by using the 2-processor system 2 within the same time period needs only half the frequency and voltage, which, compared to the system 1 with one pro- cessor, results in a quarter of the power consumption. 100. Thus, Panda unambiguously and directly discloses that parallelizing one task and using a 2-processor system to process the parallelizable parts of the tasks in parallel allows for decreasing power consumption. 101. However, comparing only a single processor system architecture to a 2- or multiple-pro- cessor system architecture, Fig. 3.7 and sub-chapter 3.1.1.1 do not unambiguously and directly disclose the way of distributing several tasks across several processors in a 2- or multiple-processor system as foreseen by the patent-in-suit. Even though Panda has a chapter 2 on “Basic Low Power Digital Design” that inter alia contains some basics on voltage and frequency scaling (sub-chapter 2.3.4, p. 28 et seqq.) including Dynamic Volt- age and Frequency Scaling DVFS (sub-chapter 2.3.4.3, p. 30) and some basics on clock gating (sub-chapter 2.3.3, p. 25 et seqq.), Fig. 3.7 and sub-chapter 3.1.1.1 do also not unambiguously and directly disclose that DVFS or a clock gating unit is used in this con- text, in particular when processing a task that has been parallelized, let alone in the con- text of distributing the processing of several tasks across multiple processors. 102. Furthermore, Panda does not unambiguously and directly disclose to apply Fig. 3.7 and sub-chapter 3.1.1.1 to interrupts in all the respects discussed above. 103. Even more so, Panda does not unambiguously and directly disclose an IID that distributes an interrupt received to one of the first and the second processors which is in an idle state (feature 7) and that dynamically adjusts the operating frequency and voltage in accord- ance with feature 8. Inventive step starting from Panda in combination with general common knowledge 104. It can be left open whether Panda is a suitable starting point, given its content discussed supra. Even if the features 1 to 7 as a basic configuration were known as part of the gen- eral common knowledge (GCK) as alleged by Defendants, the subject-matter of claim 1 would involve an inventive step starting from Panda in combination with GCK. 32 105. It is not apparent why the skilled person is motivated by Panda or otherwise • to transfer Panda to the handling of interrupts, o thereby, from the comparison of processor system architectures, deriving not only a way of handling a single task or interrupt by distributing its processing across several processor, but also a way of handling several tasks or interrupts, o slowing down the frequency of the processors despite the fact that interrupts – in contrast to tasks – are urgent by nature and call for immediate processing, • to foresee a functional entity that o is able to distribute the interrupt or task to an idle processor and, o in addition, in this context, is able to adjust in terms of controlling dynamically the operating frequency and voltage of the processors (instead of foreseeing a general power management entity that in general manages the power by react- ing to a given workload in terms of adjusting, in particular lowering frequency and voltage, if needed or possible), o by sending commands to the clock gating unit o in order to maintain a throughput that is the same as that for an equivalent single processor system instead of using the additional processors to speed up the processing in light of their urgent nature when several interrupts occur. 106. In particular, the unspecific statement in the paper by Gountanis et al (exhibit D CC 16) invoked by Defendants as evidence for GCK in their Reply only (Reply-CCR, para. 32) that task assignment and processor selection for interrupt processing were similar problems with regard to optimum priority response, expressly entailing a fast execution far from the purpose of claim 1 (exhibit D CC 16, page 1813, left col., third para. and page 1818, first para. in section 4.1), does not prompt the skilled person to transfer every policy for task handling to interrupt handling without further ado. It can be therefore left open whether exhibit D CC 16 is late filed, as Claimant complains. 107. Apart from that, contrary to Defendants’ view, it cannot be established that the alleged basic configuration comprising features 1 to 7 is known from the GCK. It is not sufficient 33 that all individual elements for themselves may be part of the GCK. Rather, the specific combination thereof as laid down in the patent claim has to be part of the GCK as well. Defendants failed to substantiate that this is the case for the alleged basic configuration. When relying on the allegation that the skilled person would arrive at a certain design when applying general known principles and combining general known elements, it has to be demonstrated that the skilled person would inevitably arrive at such design without applying inventive steps. Applying these principles, Defendants have not sufficiently demonstrated why the skilled person would arrive at the design shown in Fig. 3 of the private expert opinion in exhibit D CC 3 without hindsight. In particular, it is not obvious, why it is the interrupt controller which is also tasked with the power management of the processors and not a different entity that is independent from the interrupt controller and that manages the power in general in response to the workload of the processors. 108. Furthermore, the private expert opinion of Defendants is not suitable to demonstrate that its Fig. 3 is the result of applying GCK. As discussed supra, the author of the private expert opinion is qualified in a way that goes far beyond the knowledge and ability of the skilled person. Therefore, it is required to demonstrate for every single step in the line of thoughts that it is rooted only in GCK the relevant piece of which has to be specifically named and demonstrated. This also applies to every combination of pieces of GCK. Inventive step starting from Wolfe (US 8,260,996 B2; exhibit D CC 4) in combination with Panda Disclosure of Wolfe 109. Defendants invoke Wolfe for the disclosure of features 1 to 7. However, Wolfe at least lacks direct and unambiguous disclosure of features 4, 6.4 and 8. 110. Wolfe relates to interrupt optimization for multiprocessors when allocating interrupts within a multiprocessor computing system among several processors or cores respec- tively. It discloses in Fig. 8 a multi-processor system. For ease of reference, Fig. 8 is de- picted in the following with colour highlights added by the Defendants (cf. SoD-CCR, para. 75). 34 111. The explanation of Fig. 8 in col. 13 lines 60 to 67 of the patent description clearly shows that Fig. 8 relates to a multiprocessor system that comprises several cores. Also depicting the other processors that are constructed and connected in the same way would only have made Fig. 8 more complex without adding any further relevant information to it. The memory bus 30 (highlighted in red) is connected via a bus/interface controller inter alia to an interface bus 942 (highlighted in blue) which is connected inter alia, via periph- eral interfaces 70, to peripheral devices (not shown, connection highlighted in yellow, cf. col. 14 lines 63 to 67). Fig. 8 therefore unambiguously and directly discloses not only a first processor that is undisputedly coupled to a first bus being the memory bus 30 (high- lighted in red) but, contrary to Defendants, also a second processor that is coupled to the first processor by the first bus, i.e. the memory bus 30 (features 1, 2). Furthermore, Fig. 8 undisputedly discloses with the interface bus a second bus that is coupled to the first bus (feature 3) and a first and a second peripheral device coupled to the second bus (fea- ture 5). 112. Fig. 2 discloses a multiprocessor that comprises an interrupt controller. For ease of refer- ence, Fig. 2 is depicted in the following with colour highlights added by the Defendants (cf. SoD-CCR, para. 79). 35 113. The interrupt controller 220 (highlighted in orange) is connected inter alia to external interfaces 230 and peripherals 246 (highlighted among others in yellow) by interrupt lines 225 (highlighted in turquois), as explained in the description of Fig. 2 (cf. col. 4 lines 36 et seqq., in particular lines 51 to 56). The interrupt controller is connected to the cores by an interrupt bus 215 (cf. col. 4 lines 56 to 58) that can be a serial bus, a parallel bus, or any channel for communicating signals between the interrupt controller 220 and the mul- tiple processor cores 210 (cf. col. 4 lines 58 to 61). The interrupt bus 215 may be a general- purpose system, I/O, or a memory bus that is also used for communicating signals be- tween the interrupt controller and the multiprocessor cores (col. 4 lines 61 to 64). In re- sponse to an interrupt request event, the interrupt controller 220 can identify which of the processor cores 210 is the preferred responder to the interrupt (cf. col. 5 lines 16 to 18). Fig. 2 therefore undisputedly discloses an interrupt distributor that is coupled in ac- cordance with feature 6.2 und 6.3 and that is intelligent in some way because it can iden- tify which of the processors is the preferred responder to handle the interrupt. The ex- ternal interfaces, being coupling means, do not exclude a direct coupling. It can be left open whether an external memory controller 15 between the memory bus and the con- troller (as depicted in Fig. 8) would exclude a direct coupling within the meaning of fea- ture 6.2 between elements coupled to the memory bus and the processor as such a memory controller is optional (cf. col. 14 lines 9 to 12). 114. Contrary to Claimant, Fig. 2 does not describe a separate embodiment but has to be read as being supplemented by Fig. 8. Whereas Fig. 2 explains the interrupt controller, Fig. 8 36 explains the overarching architecture of the microprocessor system in which the interrupt controller of Wolfe operates. Since Fig. 8 does only depict one processor for sake of clar- ity, it consequently does not depict the interrupt controller either. When integrating the interrupt controller into the overarching architecture of Fig. 8, in accordance with col. 4 lines 61 to 64, for the connection to the cores, a separate interrupt bus or the memory bus can be used for communicating interrupts, as discussed supra. Therefore, in addition to features 1 to 3 and feature 5 disclosed in Fig. 8, Wolfe also discloses features 6, 6.1 to 6.3. The factual assertion of Defendants that the interrupt controller is necessarily con- nected to the memory bus being the first bus (cf. SoC-CRR, para. 80) is not disputed. 115. The interrupt allocation techniques disclosed in Wolfe encompass an allocation that maintains a processor core affinity for interrupt service routines/interrupt handlers, i.e. for operations associated to the interrupt in question. By preferably allocating an inter- rupt to a processor that previously executed the specific interrupt handler as the pre- ferred processor, such a core affinity is used which can support caching efficiency (cf. col. 1, lines 37 to 42; col. 2 lines 35 to 45; col. 6 lines 1 to 3). However, in cases in which the preferred processor with core affinity that executed the previous instance of a specific interrupt is busy, the interrupt handler may alternatively be allocated to an idle core or a core that executes a low priority task (cf. col. 5 lines 56 to 66; col. 6 lines 3 to 6). For opting between these two alternatives, the caching efficiency may be balanced against the ben- efits of assigning the execution of the interrupt handler to a different core that is currently idle or processing a lower priority task (col. 1 lines 43 to 47; col. 2 lines 45 to 49; col. 5 lines 64 to 66; col. 6 lines 7 to 10). If there is no core with affinity to a specific interrupt handler, because it is executed for the first time, the interrupt controller may establish the initial preferred responder among the cores by other techniques, including inter alia assignment by a measure of the least busy core (col. 6 lines 23 to 30). 116. Against this backdrop, Wolfe unambiguously and directly discloses an interrupt controller that is able to distribute an interrupt to the second processor which is in idle state. Whether the fact that this may be a second choice because the availability and efficiency of a core with core affinity is checked first runs counter to feature 7, can be left open. 117. However, contrary to the Defendants, Wolfe does not unambiguously and directly dis- closes a clock gating unit (feature 4). Undisputedly, Wolfe does not explicitly mention clock gating or a clock gating unit. A sufficient disclosure does not follow from the fact 37 that a processor may be idle before receiving an interrupt (e.g. col. 1, line 46, col. 2, line 47, col. 5, line 64, col. 6 line 6). It is not sufficiently clear that idle does not only mean that the processor is not busy but, in addition, clock gated. Even if a clock gating unit were disclosed, a direct coupling of the interrupt controller to the clock gating unit would still not be disclosed. Since the interrupt controller of Wolfe merely allocates the interrupts to the preferred core (based on core affinity or, if not applicable or disadvantageous, based on workload), it is not apparent why the interrupt controller would need a direct coupling to a clock gating unit. Furthermore, feature 8 is undisputedly not disclosed. 118. In summary, Wolfe at least lacks disclosure of features 4, 6.4 and 8. Inventive step 119. Wolfe relates to interrupt optimization for multiprocessor when allocating interrupts and is therefore a suitable starting point. 120. However, a combination of Wolfe and Panda does not result in an implementation of all features of claim 1. Features 4, 6.4 and 8 would still be missing. 121. Furthermore, there is no motivation in Wolfe or Panda (or elsewhere) to modify Wolfe and Panda in a way that would result in the subject-matter of claim 1. First, there is no motivation to change the interrupt optimization proposed by Wolfe by forgoing the as- signment based on core affinity and, instead, assigning the interrupt to the processor, which is in idle state, and lowering frequency and voltage in accordance with feature 8. Even if a power management for the cores in accordance with DVFS were applied, there would be no motivation to task the interrupt controller with adjusting operating fre- quency and voltage and not a different entity, which is in charge of the power manage- ment in general and responds to the workload of the processors in terms of adjusting, in particular lowering frequency and voltage, if needed or possible. In consequence, even if a clock gating were to be considered, there would be no motivation to directly couple the interrupt controller to the clock gating unit, if the interrupt controller is not involved in adjusting frequency and voltage. For further details, reference is made to the reasons given in the context of Panda. 38 Inventive step starting Panda in combination with Wolfe (US 8,260,996 B2; exhibit D CC 4) 122. Defendants base an invalidity attack, starting from Panda, on the combination of Panda and Wolfe for the first time in their reply-CCR without explaining and without it being otherwise apparent why they did not raise such an attack already in their statement of claim for the counterclaim for revocation and why the subsequent assertion is not due to negligence (R. 263.2 (a) RoP). The panel does therefore not allow the attack. 123. Apart from that, changing the starting point from Wolfe to Panda does not yield a differ- ent result. The new attack would still be unsuccessful in substance for the reasons given supra. Inventive step starting from Uchiyama (exhibit D CC 5) and/or Hoang (exhibit D CC 5a) in com- bination with Panda Disclosure of Uchiyama (exhibit D CC 5) and Hoang (exhibit D CC 5a) 124. Defendants invoke Uchiyamy and Hoang for the disclosure of features 1 to 7 and of the use of frequency and voltage adjustment in the context of dynamic power management in a multiprocessor system. However, both documents do not directly and unambiguously disclose features 6.4, 7 (and possibly 6.2) and 8. 125. Uchiyama relates to heterogeneous multicore processor technologies. Chapter 4.3 dis- cusses an example of a multicore processor and discloses in Fig. 4.13 (p. 137) a multi-core chip. For ease of reference, Fig. 4.13 is depicted in the following with colour highlights added by the Defendants (cf. SoD-CCR, para. 168). 39 126. The exemplary eight processor cores (highlighted in green) are coupled inter alia to an On-chip system bus (SuperHyway) (highlighted in red) that is connected inter alia to a Global Clock Pulse Generator GCPG (highlighted in pink) and to a Peripheral Bus Bridge SPHB (highlighted in blue) that is connected inter alia to an Interrupt Controller INTC (highlighted in orange) (for the meaning of abbreviations, cf. Fig. 4.4 on p. 128 and text on p. 129). Between the SPHB and each core, a Local Clock Pulse Generator LCPG exists. In chapter 4.3.2 (p. 137, below Fig. 4.13), it is stated that “each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing per- formance while reducing the average operating power consumption” (p. 137). Chapter 4.3.4 “Interrupt handling for Multicore” (p. 140) discloses in Fig. 4.17 a block diagram of the interrupt controller INTC, depicted below (red rectangle added by Defendants, cf. SoD-CCR para. 170) and proposes an autorotating interrupt distribution scheme for dis- tributing the handling of interrupts across the cores. 40 127. In this context, fixed and dynamic distribution modes are discussed. In a fixed distribution mode, the interrupt request is distributed to the specific core configured by setting up an interrupt mask register (p. 140). In the first of two dynamic distribution modes, the so- called conventional dynamic distribution mode, the interrupt request is distributed sim- ultaneously to all the cores and will be served by the first acknowledging one (p. 140). In the second dynamic distribution mode, being the autorotating dynamic distribution mode, which reduces overhead, the INTC asserts an interrupt request to one core for some cycles specified by the software, which are at most 24 cycles. Since then the other cores need not consume the redundant interrupt handling time, Uchiyama concludes that this mode is best in terms of computing throughput and can keep the worst response time of the conventional mode, which is important in order to guarantee the response time (p. 141). 128. Against this backdrop, Uchiyama undisputedly discloses features 1-3, 5, 6, 6.1 and 6.3, wherein the On-chip system bus (SuperHyway) (highlighted in red) can be seen as first bus and the Peripheral Bus Bridge SPHB (highlighted in blue) as second bus (feature 2 und 3). It is clear that the Peripheral Bus Bridge is coupled to more than one peripheral device (feature 5). The interrupt controller INTC is coupled (via SPHB) to the On-chip system bus (feature 6.1) and is undisputedly directly coupled to more than one peripheral device via dedicated interrupt lines (feature 6.3). The interrupt controller INTC is intelligent in some way because it distributes the interrupts in accordance with a specific distribution scheme (feature 6). Contrary to the Claimant, since, as mentioned above, each processor can even 41 dynamically stop the clock, a clock gating unit in this regard exists which necessarily has to be coupled to the processors (feature 4). 129. However, contrary to the Defendants, Uchiyama does not disclose that the interrupt con- troller is able, as part of a distribution policy, to distribute an interrupt to a processor which is in idle state (feature 7). It is not sufficient, that a core the turn of which is now may be idle by accident. 130. Furthermore, Uchiyama does undisputedly not disclose feature 8. While each processor is able to operate at different frequency or even dynamically stop the clock to maintain processing performance while reducing the average operating power consumption (p. 137, cf. citation supra), it may not unambiguously and directly disclosed that the voltage is dynamically reduced. Moreover, it is not disclosed that the interrupt controller adjust the frequency and voltage in accordance with feature 8. Therefore, there is no apparent technical need for the interrupt controller to be directly coupled to the clock gating unit (feature 6.4) so that feature 6.4, which is not otherwise disclosed either, is not disclosed. Even if a core were idle and clock gated at the point in time when the interrupt controller assigns an interrupt to it, it is not unambiguously clear that the removal of the clock gating is ordered by the interrupt controller and not by another instance which initiates the re- moval of the clock gating when an interrupt arrives at a clock gated core. Uchiyama does not mention that the interrupt controller is directly coupled to the processors by an in- terrupt bus (feature 6.2). It can be left open whether the skilled person would read an interrupt bus instead of dedicated lines between the lines because opting between a ded- icated line and a bus in this context would at least not involve an inventive step. If the communication of interrupts took place by the SPHB, however, the existence of the Local Clock Pulse Generators LCPG as functional entities would exclude a direct coupling. 131. At the beginning of chapter 4.3 (p. 136), Uchiyama undisputedly refers to Hoang (exhibit D CC 5a, reference [17]). However, Hoang does not add any further aspect to the disclo- sure. It depicts Fig. 1 and Fig. 2 shown below that are similar to the figures in Uchiyama discussed supra and explains the different modes of interrupt distribution including the preferred autorotating mode in a similar way. 42 132. In particular, the single lines between the INTC and the eight cores may even point out that no interrupt bus is used but dedicated lines. Furthermore, the fact that, in the not preferred first dynamic mode in which the interrupt is handled by the first acknowledging core, some cores may be in sleep mode (Hoang, p. 196, left col. lines 3 to 5) does also not imply that it is the interrupt controller INTC that wakes up the cores and therefore needs to communicate directly with and thus to be directly coupled to a clock gating unit. 43 133. Against this backdrop, it can be left open whether Uchiyama and Hoang form a single source of disclosure. 134. In summary, features 6.4, 7 and 8 (and possibly 6.2) are not unambiguously and directly disclosed. Inventive step 135. Both Uchiyama (chapter 4.3.4 and its context) and Hoang relate to interrupt handling op- timization for multiprocessor when allocating interrupts and are therefore a suitable starting point. 136. However, a combination of Uchiyama and/or Hoang and Panda does not result in an im- plementation of all features of claim 1. Features 6.4, 7 and 8 (and possibly 6.2) would still be missing. 137. Furthermore, there is no motivation in Uchiyama, Hoang or Panda (or elsewhere) to mod- ify Uchiyama/Hoang and Panda in a way that would result in the subject-matter of claim 1. First, there is no motivation to change the preferred interrupt distribution mode (autorotating distribution) proposed by Uchiyama and Hoang by forgoing the assignment in an autorotating way and foresee a distribution policy that involves assigning the inter- rupt to the processor, which is in idle state, and lowering frequency and voltage in ac- cordance with feature 8. Similarly to the combination with Wolfe, even if a power man- agement for the cores in accordance with DVFS were applied, there would be no motiva- tion to task the interrupt controller with adjusting operating frequency and voltage and not a different entity, which is in charge of the power management in general and re- sponds to the workload of the processors in terms of adjusting, in particular lowering frequency and voltage, if needed or possible. In consequence, there would be no motiva- tion to directly couple the interrupt controller to the clock gating unit, if the interrupt controller is not involved in adjusting frequency and voltage. For further details, reference is made to the reasons given in the context of Panda that apply mutatis mutandis. 44 IV. Lack of inventive step over any asserted combination encompassing Lee (paper in exhibit D CC 2a (“Lee paper”), slides in exhibit D CC 2b (“Lee slides”)) Disclosure of Lee 138. Defendants invoke Lee for the disclosure of feature 8 (labelled “basic idea or core con- cept”). In their Reply-CCR (e.g. para. 97, 147), they refer to their submissions on Panda in the Reply-CCR would apply accordingly. However, Lee does not directly and unambigu- ously disclose feature 8, nor – should this be meant by the reference – an IID (feature 6) and a clock gating unit (feature 4). 139. Lee paper deals with parallel processing. According to Lee paper, in a many-core proces- sor system, as far as fractions of an application can be processed in parallel, the same demanded throughput can be achieved with more cores at a lower supply voltage and frequency if the (infinitely) parallelizable fractions F of the application are processed in parallel using a higher number of cores instead of being processed sequentially using one or a lower number of cores running at maximum frequency and voltage to meet the de- manded throughput. This parallel processing at lower supply voltage and frequency leads to a significant amount of dynamic and leakage power reduction (cf. D CC 2a, p. 202 sub- section 2.1 Supply power scaling, first two paragraphs). 140. Lee paper therefore unambiguously and directly discloses that, in a many-core processor, parallel processing of parallelizable fractions of an application by using more cores can maintain the same demanded throughput at lower power consumption compared to us- ing only one or fewer cores at higher voltage. 141. Lee slides also deal with parallel processing (cf. exhibit D CC 2b, p. 2 slide “Multicore pro- cessors”: “parallel processing”). The slide “Supply Voltage Scaling” on p. 2 of exhibit D CC 2b (depicted infra) discloses that using more cores at lower voltage could achieve the same throughput as using a certain (lower) number of cores at maximum voltage, whereby a lower voltage reduces power consumption. 45 142. At first sight, it might be doubtful whether the slide depicted supra from Lee slides relates only to a comparison of many-core processors with a different number of cores to each other or also to a comparison concerning the use of a different number of cores in the same many-core processor. However, it follows unambiguously and directly from its cap- tion “Supply Voltage Scaling”, that the slide also relates to the use of a different number of cores within a single multi-core processor system. As not disputed by the parties, the disclosure of Lee Slides corresponds to that of Lee paper. 143. Neither Lee paper nor Lee slides unambiguously and directly disclose the handling of sev- eral applications, let alone interrupts. In particular, they do not disclose the parallelization of one interrupt, let alone a distribution of several interrupts across several cores at dy- namically adjusted lower frequency and voltage in order to maintain the throughput of an equivalent single-core processor (feature 8). 144. Even more so, both Lee paper and Lee slides do not unambiguously and directly disclose an IID that distributes an interrupt received to one of the processors which is in an idle state (feature 7) and that dynamically adjusts the operating frequency and voltage in ac- cordance with feature 8. Although Lee may disclose frequency scaling, Defendants did not demonstrate that it also discloses a clock gating unit that is able not only to scale frequency but also to entirely block the clock and that is connected with and working together with an IID in accordance to claim 1. 46 145. Against this backdrop, notwithstanding their closely corresponding disclosure, it can be left open whether Lee paper and Lee slides constitute a single source of disclosure and can therefore be read together. Inventive step starting from Lee in combination with general common knowledge 146. Even if the features 1 to 7 as basic configuration were known as part of the general com- mon knowledge (GCK) as alleged by Defendants, the subject-matter of claim 1 would in- volve an inventive step starting from Lee paper or Lee slides, even if seen as single source of disclosure, in combination with GCK. 147. Analogously to what is said for Panda, it is not apparent why the skilled person is moti- vated by Lee or otherwise • to transfer Lee to the handling of interrupts, o thereby, from the comparison of parallel processing of an application using a higher or lower number of cores, also deriving a way of handling several appli- cations or interrupts, o slowing down the frequency of the processors despite the fact that interrupts – in contrast to applications – are urgent by nature and call for immediate pro- cessing, • to foresee a functional entity that o is able to distribute the interrupt or application to an idle processor and, o in addition, in this context, is able to adjust in terms of controlling dynamically an operating frequency and voltage of the processors (instead of foreseeing a general power management entity that in general manages the power by react- ing to a given workload in terms of adjusting, in particular lowering frequency and voltage, if needed or possible), o by sending commands to the clock gating unit, 47 o in order to maintain a throughput that is the same as that for an equivalent single processor system instead of using the additional processors to speed up the processing in light of their urgent nature when several interrupts occur. 148. Apart from that, for the reasons given supra in the section regarding Panda, it cannot be established that the basic configuration comprising features 1 to 7 is known from the GCK. Inventive step starting from Wolfe (US 8,260,996 B2; exhibit D CC 4) in combination with Lee 149. Similar to Panda, a combination of Wolfe and Lee does not result in an implementation of all features. Features 4, 6.4 and 8 would be still missing. 150. For the lack of motivation, starting from Wolfe, to change a combination of Wolfe and Lee, the reasons given supra with regard to Panda apply mutatis mutandis. Lee does not add any further aspect that would justify a different result. In particular, it is still not ob- vious to task the interrupt controller with adjusting operating frequency and voltage and not a different entity, which is in charge of the power management in general and re- sponds to the workload of the processors in terms of adjusting, in particular lowering frequency and voltage, if needed or possible. Inventive step starting from Uchiyama (exhibit D CC 5) and/or Hoang (exhibit 5a) in combina- tion with Lee 151. Similar to Panda, a combination of Uchiyama and/or Hoang and Lee does not result in an implementation of all features. Features 6.4, 7 and 8 (and possibly 6.2) would still be missing. 152. For the lack of motivation, starting from Uchiyama and/or Hoang even when considered as a single source of disclosure, to change a combination of these documents and Lee, the reasons given supra with regard to Panda apply mutatis mutandis. Lee does not add any further aspect that would justify a different result. In particular, it is still not obvious to task the interrupt controller with adjusting operating frequency and voltage and not a different entity, which is in charge of the power management in general and responds to the workload of the processors in terms of adjusting, in particular lowering frequency and voltage, if needed or possible. 48 V. Lack of inventive step over any asserted combination encompassing Belleudy (exhibit D CC 6; English translation in exhibit D CC 6a) Disclosure of Belleudy 153. The Defendants invoke Belleudy for the disclosure of feature 8 (labelled “basic idea or core concept”). However, Belleudy does not directly and unambiguously disclose fea- ture 8. 154. Belleudy deals with multiprocessor architecture and low power consumption. It discloses Voltage and Frequency Scaling VFS in the context of processing within deadlines in slides 20 to 24 that belong to chapter 2.1 on consumption management mechanism on the pro- cessor side. In this context, for a single processor, Belleudy describes that frequency f and voltage V and thus power consumption can be lowered, if the processing of a Task Ti is decelerated by lowering the frequency from f1 to f2 provided that the deadline for com- pleting the processing of this task is still met (cf. slide 20). In slides 21 and 22, Belleudy discloses VFS Scheduling within a hyperperiod when a EDF-policy, meaning Earliest Dead- line First-policy (cf. definition in slide 12), is in place for a single and a multiple processor case, thereby calculating a deceleration factor S – based on the workload U, given by the periods of the tasks T1 and T2 (and T3 respectively) and the Worst Case Execution Time (WCET) Ci of Task Ti, cf. definitions in slides 10, 11 – that corresponds to a deceleration resulting in filling-up a given hyperperiod. Slide 23 addresses Dynamic Voltage and Fre- quency Scaling that takes into account the actual (real) execution time (AET) Ai of Task Ti (cf. definition in slide 11) instead of the Worst Case Execution Time (WCET) Ci. Slide 29 discusses the energy consumption of the two alternatives of decelerating processing of Task T1 (processed by a single processor) by using VFS and of, instead of decelerating the processing to save energy, putting the processor to an energy saving idle state for the remainder of the deadline after the processing of Task T1 has been completed. 155. Slides 64 to 67 relate to dynamic scheduling and Dynamic Voltage and Frequency Scaling (DVFS) in a multiprocessor system. Several Tasks Ti that shall be processed within a certain deadline are ordered in terms of decreasing Worst Case Execution Time WCETi and dis- tributed across two processors. If the Actual Execution Time AETi of Task Ti is shorter than its WCETi the processing of the respective Task Ti can be slowed down dynamically during 49 its processing without violating the deadline (cf. slide 67) which saves power/energy in accordance with the principles addressed in slides 20 to 24. 156. Slide 56 named “Plateforme Multiprocesseur: MPcore” shows the following schematic representation: 157. Slide 57 shows the power consumption at different working points (possible pairs of fre- quency and voltage values) when using none or up to and including 4 active cores. The table discloses that frequency and voltage are positively correlated among each other and to power consumption, i.e. both frequency and voltage increase or decrease and power consumption increases or decreases with increasing or decreasing frequency and voltage. 158. Against this backdrop, Belleudy does not disclose to distribute a task to an idle processor and adjust frequency and voltage in this context to maintain a throughput that is the same as in a single processor system. Rather, Belleudy discloses that the processing of a task is decelerated within a given deadline (by lowering the frequency and, in this context, the voltage resulting in less power consumption) or, in the alternative, the frequency/pro- cessing speed is maintained and the processor is put to a power/energy saving idle mode for the remainder of the deadline after the processing of the task has been completed, depending on what alternative is favorable in terms of power/energy consumption 50 (cf. slide 29). This principle can be applied both to a single processor and to a multipro- cessor system (cf. slide 21, 22, 64-67). 159. Apart from that, Belleudy does not unambiguously and directly disclose that the handling of tasks can be applied to interrupts. 160. Belleudy discloses an interrupt distributor (cf. slide 56) and may disclose the relationship between frequency and voltage and power consumption and this relationship may be familiar to the skilled person anyway. However, Belleudy does neither unambiguously and directly disclose an IID nor a clock gating unit that is able not only to scale frequency but also to entirely block the clock and that is connected with and working together with the IID in accordance to claim 1, wherein the IID distributes an interrupt received to one of the first and the second processors which is in an idle state (feature 7) and dynamically adjusts the operating frequency and voltage in accordance with feature 8. Inventive step starting from Wolfe in combination with Belleudy 161. Similar to Panda and Lee, a combination of Wolfe and Belleudy even when considered as a single source of disclosure does not result in an implementation of all features. Features 4, 6.4 and 8 would be still missing. 162. For the lack of motivation, starting from Wolfe, to change a combination of Wolfe and Belleudy, the reasons given supra with regard to Panda apply mutatis mutandis. Belleudy does not add any further aspect that would justify a different result. In particular, it is still not obvious to task the interrupt controller with adjusting operating frequency and volt- age and not a different entity, which is in charge of the power management in general and responds to the workload of the processors in terms of adjusting, in particular low- ering frequency and voltage, if needed or possible. Inventive step starting from Uchiyama (exhibit D CC 5) and/or Hoang (exhibit 5a) in combina- tion with Belleudy (exhibit D CC 6) 163. Similar to Panda and Lee, a combination of Uchiyama and/or Hoang and Belleudy does not result in an implementation of all features. Features 6.4, 7 and 8 (and possibly 6.2) would still be missing. 51 164. For the lack of motivation, starting from Uchiyama and/or Hoang even when considered as a single source of disclosure, to change a combination of these documents and Belleudy, the reasons given supra with regard to Panda apply mutatis mutandis. Belleudy does not add any further aspect that would justify a different result. In particular, it is still not obvious to task the interrupt controller with adjusting operating frequency and volt- age and not a different entity, which is in charge of the power management in general and responds to the workload of the processors in terms of adjusting, in particular low- ering frequency and voltage, if needed or possible. VI. Lack of inventive step over GCK 165. It is not sufficient that several or even all elements, functionalities and technical relations are known in the prior art including the GCK. Rather, it is in principle decisive for lack of inventive step that the relevant skilled person has an incentive to combine the elements, functionalities and technical knowledge in a way that results in the subjective-matter of the patent without applying hindsight. 166. Against this backdrop, the explanation in the statement of claim for the counterclaim of revocation relating to alleged GCK and the additional explanation in the Reply to the de- fence to the counterclaim for revocation do not add any further aspect that leads to a result different from that discussed supra. In particular, it is at least still not obvious to task the interrupt controller with adjusting operating frequency and voltage and not a different entity, which is in charge of the power management in general and responds to the workload of the processors in terms of adjusting, in particular lowering frequency and voltage, if needed or possible. VII. Dependent claims 167. The subject-matter of the dependent claims involves an inventive step because of the inventiveness of the subject matter of claim 1. E. IMPLEMENTATION OF CLAIM 1 BY THE ATTACKED EMBODIMENTS 168. Contrary to Claimant’s view, the attacked embodiments do not implement at least fea- ture 8 of claim 1 of the patent-in-suit. 52 169. In an infringement action, if the defendant disputes the implementation of a feature of the patent claim in a relevant manner, the claimant must represent specific facts about the design of the attacked embodiment, which, if these facts are proven, would lead to the assessment that the feature in question is implemented. The required degree of spec- ification and substantiation depends on the degree of substantiation with which the de- fendant disputes the implementation. This follows from the general obligation of the par- ties to substantiate their case, a principle that is in line with Art. 54 UPCA and reflected inter alia in R. 13.1 (l) (n), R. 24 (e) (g) RoP. 170. The Defendants stated that the attacked embodiments do not implement the possibility of operating in accordance with feature 8, in particular, as a pre-requisite, do not imple- ment the possibility of changing voltage during operation. Against this backdrop, Claim- ant did not sufficiently substantiate with facts that the attacked embodiments can change the voltage during operation, let alone in accordance with feature 8. As specifically demonstrated by the Defendants and, apart from that, confirmed by Claimant’s own test reports (exhibit C 19), none of the aspects invoked by the Claimant constitutes a sufficient substantiation and allows for a conclusion to the effect that feature 8 is implemented. 171. This is applicable to the attacked products that contain an ARM Cortex-A53 module, as exemplified by the attacked product AM62Ax SitaraTM. 172. The fact that the ARM Cortex-A-architecture (cf. exhibit C 7b, in particular chapter 15.2, chapter 14 (p. 204, 207)) provides for the implementation of Dynamic Voltage and Fre- quency Scaling DVFS, in particular has supply rails that are suitable for this purpose, is not conclusive for the attacked embodiments implementing the possibility of dynamically changing the voltage during operation, let alone that a routine is implemented that allows for adjustments by an IID in accordance with features 7 and 8. As discussed supra in the section on claim construction, the routines that would constitute an infringement must already be implemented to realize these features with regard to the term “operable”. In particular, Claimant did not sufficiently substantiate that the transition from idle mode prompted by a core wakeup event or the transition from the clock gated WFI (Wait for Interrupt) mode prompted by an interrupt (cf. exhibit C 7b, in particular chapter 15.1) involve adjusting the voltage, let alone dynamically adjusting it in accordance with fea- tures 7 and 8. Neither did Claimant state any empirical test that shows such an adjust- ment, nor did it specify any routine implemented in the attacked embodiments which 53 would allow for such an adjustment. The same applies to (the not invoked) WFE (Wait for Event) mode and to the adjustment of OPP (Data sheet AM62Ax, exhibit C 6a, table 7.2 (p. 83)), for which Defendants stated that, during operation, only the frequency can be changed and the voltage is fixed. This is in line with the fact that the Technical Reference Manual of the attacked product AM62Ax SitaraTM only mentions Dynamic Frequency Scal- ing DFS, but not Dynamic Voltage and Frequency Scaling DVFS (exhibit C 6b, chapter 6.2.3.1 (p. 353)), and with the further fact that the AM62Ax Software Development Kit (SDK) points out that DFS uses the same OPP table with the voltages removed from the OPP tables (exhibit D4, p. 5). Even if DVFS were implemented, Claimant would have not sufficiently substantiated that the frequency and voltage were adjusted by the GIC-500 in the context of distributing an interrupt to an idle processor and in accordance with fea- ture 8. Furthermore, as discussed supra in the section on claim construction, it would not be sufficient if the GIC-500 were merely capable of distributing an interrupt to an idle processor in order to avoid using a busy processor and increasing its frequency (and volt- age) accordingly. Rather, the GIC-500 would have to be able to distribute the interrupt to an idle processor and, in this context, reducing the frequency and voltage accordingly to maintain the same throughput as if the interrupt were processed with the single busy processor. 173. The fact that Power Management Integrated Circuits (PMICs) of Defendants that are used in and compatible with the attacked embodiments allow for DVFS is not conclusive as to the capabilities of the attacked embodiments themselves. The Defendants undisputedly stated that the PMICs in question are designed to be compatible with a variety of proces- sors including such processors that have implemented DVFS such as NXP’s i.MX 8M Plus SoC (cf. Defendants’ brief dated 11 June 2025, para. 43). Therefore, the PMICs are de- signed to be proficient in DVFS in case that they are operated together with a processor that uses this functionality. 174. To the contrary, the attacked AM62A AI vision processor (falling within the category with ARM Cortex-A53) being able to dynamically change/scale the voltage during operation is rebutted by Claimant’s own test reports (exhibit C 19). The test reports and Claimant’s submissions in this regard are to be rejected as late filed, as far as Claimant bases its case on them because they go beyond a mere response to Defendants’ submission on AVS Class 0 in their rejoinder as (preliminarily) allowed by order of 14 May 2025 54 (App 18493/2025). However, they can be taken into account as far as they are counter to the conclusiveness of Claimant’s infringement action. According to the test reports, Claimant’s private experts found no pre-provided software implemented in AM62A that allows for the dynamic scaling of voltage during operation (cf. exhibit C 19, para. 12). Even if it were legally relevant that the private experts managed to implement software that changes the voltage during operation, such changes would be restricted to merely (man- ually) changing the voltage. Therefore, even with the changes to its software, the attacked embodiments were still not be able to operate in accordance with features 7 and 8 be- cause the required routines were still not implemented. Apart from that, it is unclear whether the changes made by the Claimant’s private experts are not detrimental to the functioning of the attacked embodiments in a way that excludes their use as micropro- cessors. 175. Claimant’s submissions on the AM67x product that has been introduced with the brief of 16 April 2025 (cf. supra) does not add any further decisive aspect that would lead to a different assessment. Defendants alleged that AM67x processors were not capable of AVS, that the passage in exhibit C 17 (p. 2, last para.) invoked by Claimant (as further evidence) that may point to the opposite were an error and that the sole relevant docu- ment as to the capabilities of AM67x processors were the data sheet (exhibit D13). Even if this were not true and the passage invoked by Claimant were applicable to AM67x and, mutatis mutandis, to other attacked products with ARM Cortex-A53 module, Claimant still would have not sufficiently substantiated that the attacked embodiments were capa- ble to adjust the voltage during operation, let alone in accordance with feature 7 and 8. The last paragraph on page 2 of Appendix C 17 merely states that the voltage can be changed after booting so that different voltages can be used for booting and the post- boot phase. This does not imply that the voltage selected for the post-boot phase can be changed dynamically during operation in the product as shipped without further ado. 176. No other result applies to attacked products that contain an ARM Cortex-A72 module (exhibit C 7’ (Cortex-A-72), such as the exemplary products AM68X and AM69X, that are also based on the ARMv8-A architecture and for which the reasons outlined supra apply mutatis mutandis. The fact that the product descriptions of AM68x and AM69x products do not contain a reference to DFS does not mean that the products have implemented DVFS, even more so as the product descriptions do not mention DVFS either. 55 177. The fact that the exemplary products AM68X and AM69X (and other attacked products with the ARM Cortex-A53 or ARM Cortex-A72 processor as well) may have the function- ality AVS Class 0 does also not mean that they are configured to adjust voltage during operation. Rather, an implementation of AVS Class 0 merely shows that the voltage is statically adjusted in accordance with the silicon quality to compensate for performance differences – when applying the same voltage – between individual units of the same product model, caused by natural variability in the manufacturing process. While AVS Class 0 may not exclude dynamic voltage scaling during operation, in particular not DVFS, because it may provide AVS-corrected voltages for every possible OPP (if dynamic voltage scaling or DVFS is implemented), it is no sign for these capabilities either. In addition, Claimant again did not substantiate that any dynamic adjustment in this context would be controlled by the GIC-500, let alone in accordance with feature 8. Apart from that, Claimant’s own test reports discussed supra (exhibit C 19), state for the AM69x AI vision processor as well that no pre-provided software is found that would perform dynamic voltage scaling. Moreover, no pre-provided software was found that would perform fre- quency scaling (exhibit C 19, para. 15). The same is true for the J721E/TDA4VM/DRA829V processor (exhibit C 19, para. 18). 178. With regard to the range of voltages (MIN, NOM, MAX) mentioned in the table in section 7.3 of the data sheet for the product AM68x (exhibit C11a, p. 101 et seq.) and the table of section 7.4 of the data sheet for the product AM69x (exhibit C11b, p. 138), Defendants state that the range were merely defining the permitted operation tolerance for the fixed voltage of the device, i.e. the range in which the fixed voltage may deviate from the nom- inal operating voltage without endangering safe operation. Against this backdrop, Claim- ant does not sufficiently substantiate with facts that the products implement an adjust- ment of voltage during operation. The fact that the Defendants provide a so called “Power Estimation Tool” (exhibit C 13) which allows customers to calculate the power consump- tion for various OPP also does not allow the conclusion to be drawn that the voltage is adjustable during operation without further ado. As Defendants stated without Claimant presenting facts to the contrary, the tool is intended to be used as simulation tool to es- timate the power consumption of a particular device based on its unique AVS voltage setting and other inputs. 56 179. The Application Report on Adaptive (Dynamic) Voltage (Frequency) Scaling – Motivation and Implementation (exhibit C 10) does not yield a different result. It explains DVFS and AVS (cf. section 2.6 and 2.2) and some basics on implementing them (section 4), thereby focusing in section 4, as far as specific products are concerned, on PMICs, i.e. the power supply side (p. 7 and 8 at the bottom, cf. also conclusion on p. 9 and abstract on p. 1). However, it does not relate specifically to the attacked embodiments. Moreover, in the one example given in section 4 on p. 7 at the bottom, the voltage CORE is kept constant because it has only one operating point and would therefore only require AVS. 180. Finally, there is no need to appoint a court expert given the fact that the Claimant has not sufficiently substantiated that the attacked embodiments have implemented a possibility of dynamically adjusting the voltage during operation. Even if this were the case or if the attacked embodiments even implemented DVFS, the Claimant has not substantiated that the adjustment were in accordance with feature 8, i.e. in particular that the GIC-500 has an operating mode in which it distributes a received interrupt to the idle processor and adjusts operating frequency and voltage in order to maintain a throughput that is the same as that for an equivalent single processor system. In this context, appointing a court expert to examine the attacked embodiments would result in a fishing expedition. For the same reasons, there is no need to allow Claimant to improve its case by now commission- ing a private expert to carry out such an examination. 181. Against this backdrop, it can be left open whether the GIC-500 of the attacked embodi- ments sends commands within the meaning of feature 8 to a clock gating unit and whether it is directly coupled to the clock gating unit within the meaning of feature 6.4. The same is true for the question as to whether alleged infringing acts were attributable to all Defendants. 182. As already discussed supra, the amendment to the case made in the oral hearing that aims at basing the infringement action in addition on an indirect infringement is not ad- missible. However, an indirect infringement would not be founded either. Claimant has not demonstrated that Defendants know or should have known that ultimate users may put the invention into effect by modifying the attacked embodiments in such a way that they realize features 7 and 8 in particular. Claimant pointed out that data sheets of at- tacked embodiments were stating that they provided different voltage levels for the sup- 57 ply and that this supply level could be changed by changing the PMIC configuration regis- ter. In addition, Claimant pointed out that the attacked embodiments were able to com- municate with the PMIC (cf. brief of 28 May 2025, para. 13 with reference to exhibit C 19, paras. 11, 14, 17). However, contrary to Claimant, this does not establish an instruction by Defendants to dynamically adjust the voltage during operation, let alone to implement DVFS or even features 7 and 8. It shows at most that the attacked embodiments can be operated at different voltage levels that may be statically chosen. Furthermore, Claimant did not present any reason why an ultimate user should manipulate an attacked embod- iment to make it DVFS-capable instead of purchasing processors in which this functional- ity is already implemented. Apart from that, as already mentioned, Claimant’s submis- sions in this regard go beyond what was preliminarily allowed for by the order of 14 May 2025, i.e. a response to Defendants’ submission on AVS Class 0 in their rejoinder. For this reason, the panel rejects the excess submissions of Claimant. F. LEGAL CONSEQUENCES 183. In consequence, both the infringement action and the counterclaim for revocation are dismissed. It can therefore be left open whether the Claimant is the actual owner of the patent-in-suit. G. COSTS 184. The decision on the (recoverable) costs with regard to both the infringement action and the counterclaim for revocation is based on Art. 69 (1) (2) UPCA, R. 118.5 RoP. 185. Since both Claimant’s infringement action and Defendants’ counterclaim for revocation have been unsuccessful, the court orders no reimbursement of costs. Instead, each side shall bear its own costs including the court fees incurred by them. This also includes costs incurred by any ancillary proceedings. H. VALUE IN DISPUTE 186. After hearing the parties, the value in dispute for the entire proceeding is set at EUR 10.000.000,00 (EUR 5.000.000,00 each for the infringement action and the counter- claim for revocation). This corresponds to the uncontested statements made by the re- spective claimant. 58 DECISION: 1. The infringement action is dismissed. 2. The counterclaim for revocation is dismissed. 3. The Claimant shall bear the court fees of the infringement action and the Defendants shall bear the court fees of the counterclaim for revocation. Otherwise, the parties shall bear their own costs. 4. The value in dispute for the proceeding in its entirety is set at EUR 10.000.000,00. Delivered in Mannheim on 9 October 2025 NAMES AND SIGNATURES Presiding judge Tochtermann Legally qualified judge Böttcher Legally qualified judge Zana Technically qualified judge Scilletta For the Sub-Registrar: Kranz, Clerk LD Mannheim Information about appeal An appeal against the present Decision may be lodged at the Court of Appeal, by any party which has been unsuccessful, in whole or in part, in its submissions, within two months of the date of its notification (Art. 73(1) UPCA, R. 220.1(a), 224.1(a) RoP). 59 Information about enforcement (Art. 82 UPCA, Art. Art. 37(2) UPCS, R. 118.8, 158.2, 354, 355.4 RoP) The decision has no enforceable content.

Key Holdings

• In an infringement action, if the defendant disputes the implementation of a feature of the patent claim in a sufficiently substantiated manner, the claimant must submit specific facts about the design of the attacked embodiment, which, if these facts are proven, would lead to the assessment that the feature in question is implemented. The required degree of specification and substantiation depends on the degree of substantiation with which the defendant disputes the implementation.
• Regularly, it cannot be expected from a defendant to defend himself against an assertion of indirect infringement that is raised in the oral hearing for the first time on the spot. In consequence, granting leave for such an amendment is regularly to be excluded, according to R. 263.2 (b) RoP and the right to defence.
• When invoking general common knowledge (GCK) with regard to a certain subset of the features of a patent claim, it is not sufficient that all individual elements for themselves may be part of the GCK. Rather, the specific combination thereof as laid down in the patent claim has to be part of the GCK as well.
• When relying on the allegation that the skilled person would arrive at a certain design that realizes a subset of the features of the patent claim when applying general known principles and combining general known elements, it has to be demonstrated that the skilled person would inevitably arrive at such design without applying inventive steps.

Tags

• Common General Knowledge
• Indirect Infringement
• Infringement
• Inventive Step
• Patent Amendment

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